Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology

In this paper we have proposed efficient designs of low power high speed D-latch designed using stacked inverter and sleep transistor based on 32nm CMOS technology. We have designed and simulated these circuits in HSpice simulation tool. In this simulation we have modified W/L ratio of each transistor in the circuit. We have taken power supply of 0.9V. We have calculated average power consumed propagation delay and power delay product. 

by Lalitesh Singh | Surendra Bohra"Design of Low Power High Speed D-Latch Using Stacked Inverter and Sleep Transistor at 32nm CMOS Technology" 

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd14138.pdf 

Direct URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14138/design-of-low-power-high-speed-d-latch-using-stacked-inverter-and-sleep-transistor-at-32nm-cmos-technology/lalitesh-singh

high impact factor, ugc approved journals for engineering, special issue publication

Optimizing Strength of A Retaining Wall By Altering Reinforcement Details

Retaining walls are structures designed to restrain soil to a slope that it would not naturally keep to (typically a steep, near-vertical or vertical slope). The most important consideration in proper design and installation of retaining walls is to recognize and counteract the tendency of the retained material to move downslope due to gravity. This creates lateral earth pressure behind the wall which depends on the angle of internal friction (phi) and the cohesive strength (c) of the retained material, as well as the direction and magnitude of movement the retaining structure undergoes. 

Lateral earth pressures are zero at the top of the wall and '“ in homogenous ground '“ increase proportionally to a maximum value at the lowest depth. Earth pressures will push the wall forward or overturn it if not properly addressed. Also, any groundwater behind the wall that is not dissipated by a drainage system causes hydrostatic pressure on the wall. The total pressure or thrust may be assumed to act at one-third from the lowest depth for lengthwise stretches of uniform height. 

Unless the wall is designed to retain water, It is important to have proper drainage behind the wall in order to limit the pressure to the wall's design value. Drainage materials will reduce or eliminate the hydrostatic pressure and improve the stability of the material behind the wall. Drystone retaining walls are normally self-draining. As an example, the International Building Code requires retaining walls to be designed to ensure stability against overturning, sliding, excessive foundation pressure and water uplift; and that they be designed for a safety factor of 1.5 against lateral sliding and overturning. 

The main aim of this study is to see behaviour and analysis of retaining wall with the different reinforcement detailing using software. Performing different practical model test. Comparison of strength and cost of retaining wall with and without altering reinforcement details. 

By Snehal V. Dewalkar | Mr. Sumit Sanghani | Mr. Siddharth Saswade | Mr. Piyush Savtekar | Mr. Shubham Sawant | Mr. Krishna Soni"Optimizing Strength of A Retaining Wall By Altering Reinforcement Details"

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd14304.pdf 

Direct URL: http://www.ijtsrd.com/engineering/civil-engineering/14304/optimizing-strength-of-a-retaining-wall-by-altering-reinforcement-details/snehal-v-dewalkar

manuscript publication, submit paper online, indexed journal

Power Factor Correction of a Single Phase AC to DC Interleaved Boost Converter using Fuzzy Logic Controller

This paper describes the design of a fuzzy logic controller using voltage output as feedback for significantly improving the dynamic performance of single phase AC to DC power factor correction interleaved boost converter by using Simulink/MATLAB software and validate the result by the 600W converter hardware. The objective of this proposed methodology is to develop fuzzy logic controller on control Power Factor Correction PFC interleaved boost AC to DC converter using Simulink/MATLAB software.

The fuzzy logic controller has been implemented to the system by developing fuzzy logic control algorithm. The design and calculation of the components especially for the inductor has been done to ensure the converter operates in continuous conduction mode. The evaluation of the output has been carried out and compared by software simulation using MATLAB software between the open loop and closed loop circuit. The simulation results are shown that voltage output is able to be control in steady state condition for single phase AC to DC power factor correction interleaved boost converter by using this methodology.

The focus of this paper involves the design and implementation of an interleaved PFC for high performance and small size, the controller design and implementation of boost DC/DC converter. Based on this, an optimal topology is selected for which an additional comparative analysis involving input line measure improvement control is conducted by using PI controller. The results of these experiments can be adapted for use in the circuit selection of high performance converters with power factor improvement circuits.

By Pranali V. Narayane | Dr. Hari Kumar Naidu | Vaishali Pawade"Power Factor Correction of a Single Phase AC to DC Interleaved Boost Converter using Fuzzy Logic Controller"

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd14459.pdf

Direct URL: http://www.ijtsrd.com/engineering/electrical-engineering/14459/power-factor-correction-of-a-single-phase-ac-to-dc-interleaved-boost-converter-using-fuzzy-logic-controller/pranali-v-narayane

multidisciplinary journal, submit paper online, indexed journal

A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction

Modern embedded processors includes both scratchpad memory (SPM) and cache memory in their architectures. SPM's are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection(SEC-DED) and SEC-DED double-adjacent error correction(SEC-DED-DAEC) and parity duplication approach. These approaches are used only error correction for less number of corrections and thus increases speed. 

This paper proposes a duplication scheme, cache-assisted duplicated SPM(CADS) to correct SEUs and SEMUs in data SPM lines detected by a low-cost error detecting code. This duplication approach does error detection in SPM which is faster than ECC providing multibit error correction. The extension is to include DMA with ring descriptors. The descriptor-based model provides the most flexibility in managing a system's DMA faster data transfers to or from Scratchpad memory. 

Asapu Harika | Mr. A. Sai Kumar Goud | Mr. Pradeep Kumar Reddy"A Scratchpad Memory with Advanced DMA for Data Transfer with Cache Assistance for Multi-bit Error Correction"

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd14354.pdf 

Direct URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14354/a-scratchpad-memory-with-advanced-dma-for-data-transfer-with-cache-assistance-for-multi-bit-error-correction/asapu-harika

best journal, manuscript submission, call for paper engineering

Performance Analysis of Higher Order Cascaded H-Bridge Multilevel Inverters

Cascade H-Bridge Multilevel Inverters are very popular and have many applications in electric utilities and for industrial drives. When these inverters are used for industrial drives directly, the Total Harmonic Distortion (THD) in the output voltage of inverters is very significant as the performance of drive depends very much on the quality of voltage applied to drive.

A Multilevel Inverter in high power ratings improves the performance of the system by reducing Harmonics. This paper presents the simulation of single phase nine level and eleven level inverters. Detailed analysis of these inverters has been carried out and compared with different loads. PWM control strategy is applied to the switches at appropriate conducting angles with suitable delays.

These different level inverters are realized by cascade H-Bridge in MATLAB/SIMULINK. The inverters with a large number of steps can generate high quality voltage waveforms. The THD depends on the switching angles for different units of Multilevel Inverters.

By Ms. Komal Shende | Dr. HariKumar Naidu | Prof. Vaishali Pawade"Performance Analysis of Higher Order Cascaded H-Bridge Multilevel Inverters"

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018, 

URL: http://www.ijtsrd.com/papers/ijtsrd14456.pdf

Direct URL: http://www.ijtsrd.com/engineering/electrical-engineering/14456/performance-analysis-of-higher-order-cascaded-h-bridge-multilevel-inverters/ms-komal-shende

research publication, ugc approved journals for engineering, special issue publication

Optimization of Scheduling in FMS using Heuristic Approaches: A Case Study

The flow shop scheduling problems are experiencing a huge eminence in this modern era of industrialization. In the present scenario we find almost every industry to be focusing prominently on the scheduling of the machines working in them, as it is a significant factor in deciding the net productivity. Nowadays almost each and every manufacturing system is involved in following a preplanned schedule of machine operation considering the demand criterion put forth.

 

Flexible manufacturing system being one of them is also following the same path. The largely increasing number of machines and jobs involved in the manufacturing operations has marked a huge complexity in their scheduling. Thus a proper scheduling technique is the only solution which can prove as an aid to the situation. Moving forth in the same direction, this thesis presents a few prominent methods to solve a flow shop scheduling problem.

Some major heuristics algorithms are the CDS algorithm, Palmer's algorithm, and NEH algorithm are considered in this paper for finding the most optimized result. A comparison between the heuristics algorithms has also been included in this thesis to make some conclusions upon their individual and cumulative efficiencies. The input parameters given in the problem are considered to be the basis while calculating the make span. To reduce the time involved in the whole process and the chances of human error in the calculations, a java programming code has also been generated.

By Gaganpreet Kaur | Gayatri Devi | Abhishek Kumar Mishra | Amarnath Kumar | Akarsh Mishra | Aditya Agrahari"Optimization of Scheduling in FMS using Heuristic Approaches: A Case Study" 

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd14336.pdf

Direct URL: http://www.ijtsrd.com/engineering/mechanical-engineering/14336/optimization-of-scheduling-in-fms-using-heuristic-approaches-a-case-study/gaganpreet-kaur

peer reviewed journal, manuscript submission, call for paper engineering

A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction

Modern embedded processors include both scratchpad memory (SPM) and cache memory in their architectures. SPM's are prone to soft errors like Single event upsets (SEUs) and Single event multiple upsets (SEMUs). For correcting soft errors, we use Error Correcting Codes (ECC) like single-error correction double-error detection (SEC-DED) and SEC-DED double-adjacent error correction (SEC-DED-DAEC) and parity duplication approach. These approaches are used only error correction for less number of corrections and thus increases speed. 

This paper proposes a duplication scheme, cache-assisted duplicated SPM(CADS) to correct SEUs and SEMUs in data SPM lines detected by a low-cost error detecting code. This duplication approach does error detection in SPM which is faster than ECC providing multibit error correction. The extension is to include DMA with ring descriptors. The descriptor-based model provides the most flexibility in managing a system's DMA faster data transfers to or from Scratchpad memory. 

By Asapu Harika | Mr. A. Sai Kumar Goud | Mr. Pradeep Kumar Reddy"A Dynamic Scratchpad Memory Collaborated with Cache Memory for Transferring Data for Multi-bit Error Correction"

Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-4 , June 2018,

URL: http://www.ijtsrd.com/papers/ijtsrd14351.pdf 

Direct URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/14351/a-dynamic-scratchpad-memory-collaborated-with-cache-memory-for-transferring-data-for-multi-bit-error-correction/asapu-harika

research papers, paper publication for engineering, conference issue publication