Security of integrated circuits (ICs) has emerged as a major concern at different stages of IC life-cycle, spanning design, test, fabrication and deployment. Modern ICs are becoming increasingly vulnerable to various forms of security threats, such as: 1) illegaluse of hardware intellectual property (IP) \IP Piracy. 2) Illegal manufacturing of IC\ IC Piracy. Designing of confidential ICs must satisfy many design rules in order to rectify the various attacks and to protect the secret data. Based on the concept of withholding information, on-chip comparisons for actual and expected response.
Obfuscation method to prevent the piracy overbuilding and reverse engineering RE. But no security against scan based attackers. This practical logic obfuscation applicable for combinational circuits and will not protect the scan attacks. In order overcome this drawback the recent works on hardware security to prevent piracy. From the security point of view, few limitations of existing method limit the security level.
Some countermeasures have been proposed in order to secure the scan technique and on-chip comparison. This method can be applicable for both sequential, combinational circuits. This proposed method can be applied for all scan testing. We implement the project using Xilinx ISE tool for Simulation and synthesis and the code is written in Verilog HDL.
By Rangu Lavanya | Dr. G. Shanmugapriya | Mr. S. Gopala Krishna"Analysis of Hardware Security to Prevent the Scan Based Attacks by using Sticky Counter"
Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-2 | Issue-3 , April 2018,
URL: http://www.ijtsrd.com/papers/ijtsrd11335.pdf
Direct URL: http://www.ijtsrd.com/engineering/electronics-and-communication-engineering/11335/analysis-of-hardware-security-to-prevent-the-scan-based-attacks-by-using-sticky-counter/rangu-lavanya
manuscript publication, submit paper online, indexed journal
